A 32-nm CMOS frequency locked loop for 20-GHz synthesis with ± 7.6 ppm resolution

Jean Francois Bousquet; Sadok Aouini; Naim Ben-Hamida; John Wolczanski

doi:10.1109/CSICS.2013.6659192

A 32-nm CMOS frequency locked loop for 20-GHz synthesis with ± 7.6 ppm resolution

Jean Francois Bousquet, Sadok Aouini, Naim Ben-Hamida, John Wolczanski

Chemical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Original language	English
Title of host publication	2013 IEEE Compound Semiconductor Integrated Circuit Symposium
Subtitle of host publication	Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013
DOIs	https://doi.org/10.1109/CSICS.2013.6659192
Publication status	Published - Nov 8 2013
Event	2013 35th IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Monterey, CA, United States Duration: Oct 13 2013 → Oct 16 2013

Publication series

Name	Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC
ISSN (Print)	1550-8781

Conference

Conference	2013 35th IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013
Country/Territory	United States
City	Monterey, CA
Period	10/13/13 → 10/16/13

ASJC Scopus Subject Areas

Electrical and Electronic Engineering
Condensed Matter Physics
Electronic, Optical and Magnetic Materials

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10.1109/CSICS.2013.6659192

Cite this

Bousquet, J. F., Aouini, S., Ben-Hamida, N., & Wolczanski, J. (2013). A 32-nm CMOS frequency locked loop for 20-GHz synthesis with ± 7.6 ppm resolution. In 2013 IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013 Article 6659192 (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC). https://doi.org/10.1109/CSICS.2013.6659192

A 32-nm CMOS frequency locked loop for 20-GHz synthesis with ± 7.6 ppm resolution. / Bousquet, Jean Francois; Aouini, Sadok; Ben-Hamida, Naim et al.
2013 IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013. 2013. 6659192 (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Bousquet, JF, Aouini, S, Ben-Hamida, N & Wolczanski, J 2013, A 32-nm CMOS frequency locked loop for 20-GHz synthesis with ± 7.6 ppm resolution. in 2013 IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013., 6659192, Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC, 2013 35th IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013, Monterey, CA, United States, 10/13/13. https://doi.org/10.1109/CSICS.2013.6659192

Bousquet JF, Aouini S, Ben-Hamida N, Wolczanski J. A 32-nm CMOS frequency locked loop for 20-GHz synthesis with ± 7.6 ppm resolution. In 2013 IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013. 2013. 6659192. (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC). doi: 10.1109/CSICS.2013.6659192

Bousquet, Jean Francois ; Aouini, Sadok ; Ben-Hamida, Naim et al. / A 32-nm CMOS frequency locked loop for 20-GHz synthesis with ± 7.6 ppm resolution. 2013 IEEE Compound Semiconductor Integrated Circuit Symposium: Integrated Circuits in GaAs, InP, SiGe, GaN and Other Compound Semiconductors, CSICS 2013 - Technical Digest 2013. 2013. (Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC).

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A 32-nm CMOS frequency locked loop for 20-GHz synthesis with ± 7.6 ppm resolution

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